1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to an electrically programmable and electrically erasable semiconductor memory device. More specifically, the present invention relates to: a semiconductor memory device obtained by arranging semiconductor memory cells each including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges; and to a display device and a portable electronic apparatus each having the semiconductor memory device. The present invention concerns a verifying operation at the time of performing a data writing/erasing process on such a semiconductor memory device.
2. Description of the Related Art
Conventionally, a flash memory is typically used as a nonvolatile memory.
In a flash memory, as shown in FIG. 22, a floating gate 902, an insulating film 907 and a word line (control gate) 903 are formed in this order on a semiconductor substrate 901 via a gate insulating film. On both sides of the floating gate 902, a source line 904 and a bit line 905 are formed by a diffusion region, thereby constructing a memory cell. A device isolation region 906 is formed around the memory cell (see, for example, Japanese Unexamined Patent Publication No. 5-304277 (1993)).
The memory cell retains data according to a charge amount in the floating gate 902. In a memory cell array constructed by arranging memory cells, by selecting a specific word line and a specific bit line and applying a predetermined voltage, an operation of rewriting/reading a desired memory cell can be performed.
In such a flash memory, when a charge amount in the floating gate changes, a drain current (Id)-gate voltage (Vg) characteristic as shown in FIG. 23 is displayed. In the figure, a solid line shows the characteristic in a writing state, and a dashed line shows the characteristic in an erasing state. When the amount of negative charges in the floating gate increases, the threshold increases, and an Id-Vg curve shifts almost in parallel in the direction of increasing Vg.
In such a flash memory, however, it is necessary to dispose the insulating film 907 for separating the floating gate 902 and the word line 903 from the functional viewpoint. In addition, in order to prevent leakage of charges from the floating gate 902, it is difficult to reduce the thickness of the gate insulating film. It is therefore difficult to effectively reduce the thickness of the insulating film 907 and the gate insulating film, and it disturbs reduction in size of the memory cell.